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Refereed
Papers: ( The following papers are copyrighted) [1] Ahmed Youssef, Mohamed Zahran, Mohab Anis, and Mohamed Elmasry, On the Power Management of Simultaneous Multithreading Processors, IEEE Transactions on VLSI (to appear).[2] Bushra Ahsan and Mohamed Zahran, Managing Off-Chip Bandwidth: A Case for Bandwidth-Friendly Replacement Policy, in The 2nd Workshop on Managed Multi-Core Systems (MMCS'09), held in conjunction with ASPLOS 2009. (pdf )[3] Mohamed Zahran and Sally A. McKee, Adaptive Block Placement Policy for Cache Hierarchies,in SMART'09:3rd Workshop on Statistical and Machine learning approaches to ARchitectures and compilaTion, held in conjunction with HiPEAC 2009. (pdf) [4] Bushra Ahsan and Mohamed Zahran, Cache Performance, System Performance, and Off-Chip Bandwidth... Pick any Two,
in 3rd workshop Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC), held in conjunction with HiPEAC 2009. (pdf) [5 ] Yufu Zhang, Ankur Srivastava and Mohamed Zahran, Chip Level Thermal Profile Estimation Using On-chip Temperature Sensors, Proc. International Conference on Computer Design (ICCD), October 2008. [6] Mohamed Zahran, Cache Replacement Policy Revisited, in The Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD) held in conjunction with the International Symposium on Computer Architecture (ISCA), 2007. (bib, pdf) [7]. Mohamed Zahran, Cache Hierarchy for 100 On-Chip Cores, Fifth Annual Boston Area Architecture Workshop (BARC), Jan 2007. (bib, pdf) [8] Mohamed Zahran, Kursad
Albayraktaroglu, and Manoj Franklin, Non-Inclusion [10] Mohamed Zahran
and Anasua Bhowmik, Bandwidth-Friendly Cache Hierarchy, in [11] Mohamed Zahran and Anasua Bhowmik, Hybrid
Compiler
and Microarchitecture [12] Francois Cantonnet, Yiyi Yao, Mohamed
Zahran and
Tarek El-Ghazawi, [13] Mohamed Zahran and Manoj Franklin, Dynamic
Thread Resizing for Speculative Multithreaded Processors, [14] Mohamed Zahran, Manoj Franklin and Renju Thomas, Confidence
Estimation for Register Value [15] Mohamed Zahran, On Cache Memory
Hierarchy for Chip-Multiprocessor, in MEDEA workshop [16] Mohamed Zahran and Manoj Franklin, Return
Address Prediction
in Speculative Multithreaded Environments, [17] Mohamed Zahran and Manoj Franklin, A
Feasibility Study
of Hierarchical Multithreading, in International Parallel and
[18] Mohamed Zahran and Manoj Franklin, Hierarchical
Multi-threading
For Exploiting Parallelism at Multiple [19] Mohamed Zahran, Ashraf Abdel-Wahab and
Samir
Shaheen, Adaptive Genetic Algorithm for Multiprocessor
Selected Presentations & Talks: [1] "Off-Chip Bandwidth: The New Wall in The Multicore Era", in CS Departmental seminar series, University of Delaware.
[2] "Cache
Replacement Policy Revisited", in The Annual Workshop on
Duplicating, Deconstructing, and [4]"RHT: A Context-Based Return
Address Predictor", at CDES 2006. [5] "Bandwidth-Friendly Cache Hierarchy", at CDES 2006. [6] "Chip Multithreading: Issues and Challenges", in the ECE departmental seminar, University of Massachusetts Amherst (pdf). [7] "Hybrid Compiler
and Microarchitecture Technique for Cache Traffic Optimization", in 9th
Workshop on Interaction between [8] " Confidence Estimation for Register Value
Communication in Speculative Multithreaded Architectures", [9] "Speculative Multithreading...The Future of
Microprocessors", [10] "Microprocessors...Can We Make Further
Progress", [11] "On Cache Memory Hierarchy for
Chip-Multiprocessor", in
MEDEA workshop, [12] "Feasibility Study of Hierarchical
Multithreading", in IPDPS Conference, Florida, 2002. |