Mohamed M. Zahran

[1]  Ahmed Youssef, Mohamed Zahran, Mohab Anis, and Mohamed Elmasry,  On the Power Management of Simultaneous Multithreading Processors, IEEE Transactions on VLSI (to appear).

[2] Bushra Ahsan and Mohamed Zahran, Managing Off-Chip Bandwidth: A Case for Bandwidth-Friendly Replacement Policy,  in The 2nd Workshop on Managed Multi-Core Systems (MMCS'09), held in conjunction with ASPLOS 2009. (pdf )

[3]  Mohamed Zahran and Sally A. McKee, Adaptive Block Placement Policy for Cache Hierarchies,in SMART'09:3rd Workshop on Statistical and Machine learning approaches to ARchitectures and compilaTion, held  in conjunction  with  HiPEAC 2009. (pdf)

[8] Mohamed Zahran, Kursad Albayraktaroglu, and Manoj Franklin, Non-Inclusion
      Property in multi-level Caches Revisited,  in the International Journal of
       Computers and Their Applications Special Issue on Techniques and Architectures
       for High Performance and Energy Efficient Computing Systems, 
       Vol 14, Num 2, June 2007. (bib, pdf)

[9] Mohamed Zahran and Manoj Franklin, RHT: A Context-Based Return Address
     Predictor, in The 2006 International Conference on Computer Design (CDES’06),
     LasVegas, 2006. (bib, pdf)

[10] Mohamed Zahran and Anasua Bhowmik, Bandwidth-Friendly Cache Hierarchy, in
     The 2006 International Conference on Computer Design (CDES’06), Las Vegas,  2006.  
     (bib, pdf)

[11] Mohamed Zahran  and Anasua Bhowmik, Hybrid Compiler and Microarchitecture
     Technique for Cache Traffic Optimization, in 9th Workshop on Interaction between
      Compilers and Computer Architectures (INTERACT 9),
      held in Conjunction with the 11th International Symposium on High-Performance
      Computer Architecture (HPCA-11), 2005. (bib, pdf)

[12]  Francois Cantonnet, Yiyi Yao,  Mohamed Zahran and Tarek El-Ghazawi,
      Productivity Analysis of the UPC Language, in 3rd International Workshop on
       Performance Modeling, Evaluation, and Optimization of Parallel and Distributed Systems
      (PMEO-PDS), to be held in conjunction with the International Parallel
       and Distributed Processing Symposium (IPDPS 2004).

[13] Mohamed Zahran and Manoj Franklin, Dynamic Thread Resizing for Speculative Multithreaded Processors,
      in International Conference on Computer Design (ICCD),
      San Jose, CA, October, 2003. (ps)(pdf) (Best Paper Award)

[14] Mohamed Zahran, Manoj Franklin and Renju Thomas, Confidence Estimation  for Register Value
     Communication in Speculative Multithreaded Architectures,  in first value prediction workshop (VPW1),
     held in conjunction with the 30th Annual International  Symposium on Computer Architecture (ISCA),
     San Diego, California, 2003. (ps)(pdf)

[15] Mohamed Zahran,  On Cache Memory Hierarchy for Chip-Multiprocessor,  in MEDEA workshop
      held in conjunction with PACT 2002 Conference,  Charlottesville, Virginia, 2002. Also Appeared in
      ACM Computer Architecture News, Vol 31, No. 1, March 2003.

[16] Mohamed Zahran and Manoj Franklin,  Return Address Prediction in Speculative  Multithreaded Environments,
      in  Int'l Conference on Hi-Performance Computing,  Bangalore, India, 2002. (ps)(pdf)

[17] Mohamed  Zahran and Manoj Franklin, A Feasibility Study of Hierarchical Multithreading, in International Parallel and 
      Distributed Processing Symposium (IPDPS 2002), Marriott Marina, Fort Lauderdale, Florida, 2002. (ps) (pdf)

[18] Mohamed  Zahran and Manoj Franklin, Hierarchical Multi-threading For Exploiting Parallelism at Multiple 
     Granularities, Workshop on MULTITHREADED EXECUTION, ARCHITECTURE and COMPILATION (MTEAC-5), 
     Austin,  Texas, 2001. (ps) (pdf)

[19]  Mohamed Zahran, Ashraf Abdel-Wahab and Samir Shaheen, Adaptive Genetic Algorithm for Multiprocessor
       Scheduling,  poster presentation at the Genetic and Evolutionary Computation Conference (GECCO), Orlando, 1999.

Selected Presentations & Talks:

[1] "Off-Chip Bandwidth: The New Wall in The Multicore Era", in CS Departmental seminar series, University of Delaware.

[2] "Cache Replacement Policy Revisited", in The Annual Workshop on Duplicating, Deconstructing, and   
      Debunking (WDDD)held in conjunction with the International Symposium on Computer Architecture (ISCA), 2007.

[3] "Attacking The Von-Neumann Bottleneck: Smart and Scalable Cache Hierarchy in The Chip Multiprocessor Era",
       IBM T. J. Watson, Feb 2007.

[4]"RHT: A Context-Based Return Address Predictor", at CDES 2006.

[5] "Bandwidth-Friendly Cache Hierarchy", at CDES 2006.

[6] "Chip Multithreading: Issues and Challenges", in the ECE departmental seminar, University of Massachusetts Amherst (pdf).

[7] "Hybrid Compiler and Microarchitecture Technique for Cache Traffic Optimization", in 9th Workshop on Interaction between
      Compilers and Computer Architectures (INTERACT 9),
      held in Conjunction with the 11th International Symposium on High-Performance
      Computer Architecture (HPCA-11), 2005.

[8]  " Confidence Estimation  for Register Value Communication in Speculative Multithreaded Architectures",
       in first value prediction workshop (VPW1) held in conjunction with the 30th Annual International  Symposium on Computer
       Architecture (ISCA),  San Diego, California, 2003.

[9]  "Speculative Multithreading...The Future of Microprocessors",
       in Electrical and Computer Engineering Graduate Students Association (ECEGSA)Graduate Student Seminar,
       Fall 2002, (BEST TALK AWARD)

[10]   "Microprocessors...Can We Make Further Progress",
       University of Maryland Graduate Research Interaction Day (GRID), Spring 2002,
       (BEST TALK AWARD)

[11]   "On Cache Memory Hierarchy for Chip-Multiprocessor", in MEDEA workshop,
        held in conjunction with PACT, Virginia, 2002.

[12]    "Feasibility Study of Hierarchical Multithreading", in IPDPS Conference, Florida, 2002.