Associate Professor of Electrical and Computer Engineering
Department of Electrical Engineering
Voice: 212-650-7889
Grove School of Engineering FAX: 212-650-8249
The City College of The City University of New York
Email: xchen@ccny.cuny.edu
Convent Ave. & 138th Street
Web: www-ee.ccny.cuny.edu/chen
New York, NY 10031
Office: Steinman Hall, T-502
Dr. Xinghao Chen joined the Department
of Electrical Engineering,
Grove School of Engineering at the City College
of the City University of New York in
September 2002. Previously, he had worked at IBM
Corp. for more than 6 years as an Advisory Engineer/Scientist, and
before that for 2 years at the Center for Advanced Information Processing
(CAIP) at Rutgers
University as a (DARPA) Assistant Research Professor. He is the principle
author of the book on Efficient Branch-and-Bound Search with Application
to Computer-Aided Design (Kluwer Academic Publishers, 1996). He holds 2 U.S. patents
issued, with 4 provisional patents pending, several publications and disclosures.
He is a Senior Member of IEEE, a Golden Core
Member of the IEEE Computer Society, and a member of ACM as well as New York Academy of Sciences.
He is also a member of the IEEE Computer
Society Test Technology Technical Council (TTTC).
He had served as the Program Chair, General Chair, and is currently serving as the Steering Committee
Chair for the IEEE North Atlantic
Test Workshop (NATW). He received
Ph.D. in Electrical Engineering
from Rutgers University in 1993.
Research Interests
VLSI Design Automation, Test and Testability Engineering, Design-for-Test,
CMOS and Advanced Circuit Technologies, Semiconductor Yield Engineering,
Software Engineering, High-Performance Microprocessor Design, and Advanced
Computer Architecture and Network.
Recent Publications
Please use the
link to view the list.
Teaching Schedule
Spring 2007
- EE457, Digital Integrated Circuits.
Tuesday & Thursday, 6:30-7:45pm.
- EE598.67, VLSI Design Project Track,
Thursday 2-4:45pm, T-615.
Fall 2006
- EE457, Digital Integrated Circuits. Monday & Wednesday, 2-3:15pm,
BH104.
- F6400, Computer-Aided Digital VLSI Circuit Design, Tuesday,
12:30-3:15pm, T-612. (Seniors with >= 3.0 GPA need department chair approval to
register.)
- EE598.66, VLSI Design Project Track,
Thursday 2-4:45pm, T-615.
- G3900 (Cancelled), VLSI Design for Testability II: Thursday, 6:30-9:15pm.
(Shianling Wu will be the instructor.)
Spring 2006
- EE457, Digital Integrated Circuits:
Tuesday & Thursday,
6:30-7:45pm, SH381.
- EE598.67, Senior Capstone Design -
VLSI Design Projects Track:
Thursday, 2-4:45pm, T615.
Fall 2005
- EE457, Digital Integrated Circuits:
Monday & Wednesday,
2-3:15pm, BH202..
- EE598.66, Senior Capstone Design -
VLSI Design Projects Track:
Thursday, 2-4:45pm, BH202.
- G3800, VLSI Design for Testability I:
Thursday, 6:30-9:15pm, SH277, (Shianling Wu is the instructor)
Office Hours
Fall 2006: Monday & Wednesday, 3:30-5pm, T-502.
VLSI Design & Engineering Laboratory
Steinman Hall, T-502
Students:
- Hassan Bajwa (PhD in EE, 2007)
- Sheng (Alan) Yu (PhD Program, Level-2)
- Jean-Bosco Mugiraneza (PhD Program, Level-1, taking leave-of-absence)
- Eric Whitenight (Undergraduate Program)
- Richa Hajela (ME in EE, 2007)
Alumni:
- Yunzhong He, ME in EE, 2006. Process engineer at B & W Tek Inc., Newark,
Delaware.
- Yanbo Tian, PhD in EE, May 2006. RF IC design engineer at Anadigics, Inc., Warren NJ.
- Jonathan Cardenas, ME in EE, February 2006. Attending the Master Program
in Financial Engineering at Baruch College and a web developer/analyst at Knoa
Software.
- Jean-Bosco Mugiraneza, ME in EE, February 2006. Assistant lecturer at
the Kigali
Institute of Science and Technology, Rwanda.
- Asad Chaudhary, Honors College, BE in Computer Engineering, May 2005. Attending School of Law at University of
Alberta, Canada.
- Hassan Bajwa, ME in EE, May 2004. Pursuing PhD at CUNY.
Innovations:
-
United States Provisional Patent Application,
City University of New York:
“Dynamic scan configuration via scan load.”
-
United States Provisional Patent Application,
City University of New York: “A
reconfigurable scan array structures.”
-
United States Provisional Patent Application, City University of New York: “Dynamic partitioning for
area-efficient multi-port memory.”
-
United States Provisional Patent Application,
City University of New York: “Architecture for improving efficiency of a
Class-A power amplifier by dynamically scaling biasing current as well as
compensating gain.”
-
United States Patents # 6,922,800
and # 6,618,826, issued on July 26, 2005 and September 9, 2003, respectively.
“Test sequences generated by automatic test pattern generation and applicable
to circuits with embedded multi-port RAMs.”
-
United States Patent Application #
20020188904, December 12, 2002.
“Efficiency of fault simulation by
logic backtracking.”
CAD Tools
- An automatic test pattern
generation (ATPG) and fault simulation for digital circuits and ICs: the
SEST package.
- Xilinx ISE WebPack (Design-Simulation-FPGA Synthesis software, free
download).
- Electronics Workbench (SPICE simulation and PCB software, free
download).
Other Useful Links
Last update: June 2, 2007